CPU Architecture & Registers
Master the inner workings of the Central Processing Unit. Learn about the Control Unit (CU), Arithmetic Logic Unit (ALU), the Fetch-Decode-Execute machine cycle, RISC vs CISC, Von Neumann vs Harvard designs, system buses, and CPU registers (PC, IR, Accumulator, MAR, MDR).
1. CPU Organization & Control Unit Dynamics
The Central Processing Unit (CPU) is the brain of the computer system, composed of three main internal components: the Control Unit (CU), the Arithmetic Logic Unit (ALU), and the Registers.
A. Internal Components of the CPU
- Control Unit (CU): Coordinates the execution of instructions. It directs the flow of signals between the CPU and other peripherals, decoding instructions using a microprogram or hardwired logic.
- Arithmetic Logic Unit (ALU): Performs all calculations (addition, subtraction, multiplication, division) and logical comparisons (AND, OR, NOT, comparisons).
- Registers: High-speed internal storage locations situated directly inside the processor chip. They operate at the CPU core speed, which is much faster than cache memory and RAM.
B. The Fetch-Decode-Execute Cycle (Machine Cycle)
- Fetch: The Control Unit retrieves the instruction from the memory address specified by the Program Counter (PC) and loads it into the Instruction Register (IR).
- Decode: The Control Unit decodes the instruction inside the IR to determine what action is required.
- Execute: The ALU performs the decoded operation (e.g., adding two numbers or comparing values).
- Store (Write-back): The result generated by the execution phase is written back to a register or memory location.
2. Special Purpose Registers (SPRs)
CPU Registers are classified into general-purpose (accessible to assembly programmers) and special-purpose registers, which have dedicated hardware functions.
| Register Name |
Abbreviation |
Primary Function & Technical Working |
| Program Counter |
PC |
Holds the memory address of the next instruction to be fetched. It automatically increments by the size of the instruction. |
| Instruction Register |
IR |
Holds the binary code of the instruction currently being executed/decoded by the Control Unit. |
| Memory Address Register |
MAR |
Holds the physical memory address that the CPU wants to read from or write data to. Connected directly to the Address Bus. |
| Memory Data / Buffer Register |
MDR / MBR |
Holds the actual data content fetched from RAM, or data waiting to be written to RAM. Connected to the Data Bus. |
| Accumulator |
AC / ACC |
Holds intermediate arithmetic and logical results. Inputs and outputs of the ALU frequently route through it. |
| Stack Pointer |
SP |
Points to the current top address of the stack memory region in RAM, used for tracking return addresses during subroutine calls. |
| Program Status Word / Flags |
PSW / FR |
Contains status bits (flags) like Carry Flag (CF), Zero Flag (ZF), Sign Flag (SF), and Overflow Flag (OF) indicating properties of the last ALU result. |
3. Architecture Models & System Buses
Computer performance depends heavily on the memory layout and the interconnecting buses.
A. Von Neumann vs. Harvard Architecture
- Von Neumann Architecture: Uses a single memory space and shared bus system for both instructions (code) and data. This leads to the Von Neumann Bottleneck, as the CPU cannot read an instruction and read/write data at the exact same time.
- Harvard Architecture: Uses physically separate memory units and separate bus lines for code and data. This allows simultaneous instruction fetch and data access, which is highly utilized in Digital Signal Processors (DSPs) and modern microcontrollers.
B. System Buses (Interconnects)
A bus is a set of parallel wires used to transmit signals between computer components:
- Address Bus: Carries the physical memory address from the CPU to the RAM/IO. Unidirectional. Width of address bus determines maximum addressable memory capacity ($2^N$ locations).
- Data Bus: Transmits actual data/instructions between memory, CPU, and IO devices. Bidirectional. Width determines processor word size (e.g., 32-bit or 64-bit).
- Control Bus: Carries control signals (read/write commands, clock pulses, interrupts) to coordinate system operations. Bidirectional.
C. Processor design philosophy: RISC vs. CISC
- RISC (Reduced Instruction Set Computer): Uses a small set of simple, uniform-length instructions. Executes most instructions in one clock cycle using pipelining. Has a large register file and relies on compilers. Examples: ARM (used in mobile phones), MIPS, RISC-V.
- CISC (Complex Instruction Set Computer): Focuses on complex instructions that can perform multiple operations (like loading from memory, adding, and storing with one instruction). Instructions have variable lengths and take multiple clock cycles. Fewer registers. Examples: Intel x86, AMD64.
Milestones in CPU Architecture Design
- 1945 — First Draft of a Report on the EDVAC: John von Neumann described a computer architecture where program data and instruction code are stored in the same memory space (<strong style="color: #e67e22; font-weight: 700;">Von Neumann Architecture</strong>).
- 1971 — Intel 4004 Microprocessor: The first commercially available single-chip microprocessor. A 4-bit CPU designed by Federico Faggin, Ted Hoff, and Masatoshi Shima.
- 1980s — Rise of RISC Architecture: Pioneered by John Cocke at IBM, David Patterson at Berkeley, and John Hennessy at Stanford. Focused on simple, single-cycle instructions to boost clock speed.
- 2000s — x86-64 64-bit Extension: AMD introduced AMD64, extending Intel's 32-bit x86 CISC architecture to 64-bit, allowing processors to address vast amounts of memory directly.
Key Questions & Answers
- Which CPU register stores the address of the next instruction to be fetched from memory?
- Program Counter (PC) . Once an instruction is fetched, the PC automatically increments to point to the next instruction in sequence.
- What is the key structural difference between Von Neumann and Harvard architectures?
- Von Neumann uses a single shared memory and bus for both instructions and data. Harvard Architecture uses physically separate memories and buses for instructions and data, avoiding the Von Neumann bottleneck.
- Which register holds the output of the ALU's latest arithmetic or logical operation?
- Accumulator (AC) . It acts as a temporary buffer for immediate calculations before they are stored back in RAM.
- What are the characteristics of RISC processors compared to CISC?
- RISC (Reduced Instruction Set Computer) uses simple instructions of fixed length that execute in a single clock cycle, relies heavily on software optimization, and has many general-purpose registers (e.g., ARM). CISC (Complex Instruction Set Computer) uses complex instructions of variable length that execute in multiple cycles, focusing on hardware-level complexity (e.g., Intel x86).
Memory Aids
- Mnemonic 1: The Machine Cycle: The four main stages of the CPU execution cycle: • F — F etch (grabs instruction from RAM) • D — D ecode (Control Unit interprets the instruction) • E — E xecute (ALU performs computation) • S — S tore (writes results back to memory/registers)
- Mnemonic 2: Register Identification: Key registers inside the CPU: • P — P rogram Counter (holds next instruction address) • I — I nstruction Register (holds current instruction being executed) • M — M emory Address Register (holds address of memory location ) • D — M emory Data Register (holds actual data read or write) • A — A ccumulator (holds intermediate results of ALU)
- Mnemonic 3: System Bus Roles: The three buses in system design: • C — C ontrol Bus (carries command signals; bidirectional) • A — A ddress Bus (carries memory locations; unidirectional from CPU ) • D — D ata Bus (carries actual content data; bidirectional)
Common Exam Traps
- Trap 1: Confusing Program Counter (PC) with Instruction Register (IR). The PC holds the address of the NEXT instruction to be executed, whereas the IR holds the CURRENT instruction that is currently being decoded/executed.
- Trap 2: Assuming the Address Bus is bidirectional. The Address Bus is strictly unidirectional (transmitting addresses only from the CPU to memory/IO devices). The Data Bus and Control Bus are bidirectional.
- Trap 3: Confusing MAR with MDR/MBR. The Memory Address Register (MAR) holds the memory *location (address)*, while the Memory Data Register (MDR) holds the actual *data value* that is written to or read from that location.
- Trap 4: Thinking CISC uses more registers than RISC. Actually, RISC uses a larger number of general-purpose registers to minimize slower memory accesses, whereas CISC has fewer registers because it supports complex instructions that access memory directly.